TL;DR
Samsung unveiled zHBM, a radical architecture that stacks high-bandwidth memory directly on top of AI accelerators, promising up to 8x the performance of today's best HBM while cutting power draw by two-thirds.
What happened
- Samsung showcased zHBM at Future of Memory and Storage 2026 (Sept 16-18, Santa Clara Convention Center), calling it an industry first.
- Conventional HBM sits beside processors on the same plane; zHBM positions memory directly above the accelerator, shrinking the data-travel distance.
- Performance claims: up to 8x the bandwidth of HBM5 (eighth-generation HBM), up to 3x better energy efficiency, and more than 50% lower thermal resistance versus HBM5.
- A customizable interlayer between memory and processor can be configured with customer-specific IP to expand capacity or boost compute performance depending on system needs.
- Samsung also revealed zNAND-O (stacked NAND via TSVs for on-device AI) and V10 BV-NAND, the industry's first V-NAND to surpass 400 vertically stacked memory-cell layers.
Why it matters
- The memory wall is AI's biggest bottleneck: processors sit idle waiting for data; stacking memory on-chip directly attacks that latency and power problem at the architectural level.
- 8x bandwidth over HBM5 would leapfrog the current roadmap, potentially reshaping the competitive landscape for Nvidia, AMD, and custom AI chip designers who depend on memory suppliers.
- 3x energy efficiency gain is strategically significant as hyperscalers face mounting pressure on data-center power budgets and cooling costs.
- The customizable interlayer gives Samsung a co-design wedge into customers' chip architectures, deepening lock-in beyond commodity memory supply.
- zNAND-O targets on-device AI, signaling Samsung is positioning for the inference-at-the-edge market (smartphones, robotics, autonomous systems) not just cloud accelerators.
What to watch next
- No commercialization timeline was disclosed: watch for Samsung to announce yield data, a production node, or a named customer partnership as signals that zHBM moves from concept to roadmap.
- Competitor responses from SK Hynix and Micron: both are deep in HBM5 and HBM5e development; a credible 8x claim will force public roadmap reactions.
- Hyperscaler and AI chip designer adoption: whether Google, Microsoft, or a custom-silicon player (Broadcom, Marvell) publicly engages with the co-design interlayer will confirm real commercial traction.
Originally published on Present of AI, a daily source-linked AI news timeline. Read the full timeline or browse the open dataset.