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Marvell Unveils Industry-First 2nm Optical Interconnect Chips for AI

TL;DR

Marvell has demonstrated the industry's first 2nm optical interconnect chips, hitting 3.2 Tbps per link and cutting power draw, a potential inflection point for how hyperscale AI clusters scale beyond current electrical interconnect limits.

What happened

  • Marvell Technology unveiled the first 2nm optical interconnect silicon, announced September 21, 2026.
  • 3.2 Tbps data speeds demonstrated, a new benchmark for chip-to-chip and rack-to-rack AI fabric throughput.
  • Reduced power consumption cited as a core design goal alongside raw bandwidth, targeting hyperscale AI cluster economics.
  • The announcement is framed as an industry first, meaning no competing vendor has publicly demonstrated 2nm optical interconnect at this node.

Why it matters

  • Interconnect is the bottleneck in large AI clusters: GPU and accelerator compute has outpaced the bandwidth and energy efficiency of the links between them.
  • 3.2 Tbps per link at 2nm process node means more bandwidth per watt, directly reducing the operating cost of training and inference at scale.
  • Hyperscalers (cloud providers building 100,000-plus accelerator clusters) face power and space constraints where optical interconnect at this density could unlock configurations that copper simply cannot support.
  • Marvell positions itself as a critical infrastructure supplier between chip designers and cloud operators, competing with Broadcom and startups like Ayar Labs in the optical I/O race.
  • A 2nm process node for optical silicon narrows the gap between photonics and leading-edge logic, suggesting co-packaged optics at frontier nodes is closer to production than previously assumed.

What to watch next

  • Customer design wins: which hyperscalers (Google, Microsoft, Amazon, Meta) announce qualification or deployment of Marvell 2nm optical interconnect in next-generation AI pods.
  • Competing responses from Broadcom, Intel, and optical specialists: whether rivals accelerate their own 2nm photonics roadmaps or announce co-packaged optics partnerships in response.
  • Power-per-terabit figures in production silicon: the demonstration claims reduced consumption, but verified shipping specs will determine real data center impact.

Originally published on Present of AI, a daily source-linked AI news timeline. Read the full timeline or browse the open dataset.