TL;DR
Architect Labs' AI system designed a working inference chip called Redwood from written spec to FPGA prototype in under two weeks, with zero human intervention below the specification line, and respecified a revised design in under 48 hours.
What happened
- Architect Labs, a San Francisco-area startup founded July 2025, unveiled Redwood, a low-power inference chip designed entirely by an AI system after two humans wrote the spec.
- The AI handled every downstream step: performance modeling, hardware description, verification, firmware, and kernels, with no human involvement below the spec line.
- Full cycle from written spec to chip running inference on Llama and Qwen models on an FPGA took under two weeks, per a paper published in August.
- A revised design was back on the FPGA in under 48 hours after the spec was changed, the more consequential number.
- The company raised a $24 million seed round led by Kindred Ventures, co-founded by Ebrahim Hussain and 19-year-old Aaditya Subedi, and has grown to 25 people.
Why it matters
- Verification quality was unusually strong: every block hit more than 95% code and functional coverage, and the first RTL drop contained zero bugs, the phase where chip projects normally bleed months.
- The 48-hour respec cycle directly attacks the core bottleneck in AI hardware: chips are locked in years before anyone knows what models will run on them, and a two-day iteration loop starts closing that gap.
- Projected ASIC performance on Samsung 8nm-class silicon claims 1.75x throughput, 1.9x lower power, and 3.4x performance-per-watt versus Nvidia Jetson Orin Nano, but these are projections from an FPGA, not fabricated silicon.
- If the numbers survive tapeout, custom accelerator design opens to companies that could never justify the headcount for a multi-year chip program, a structural shift in who can build AI hardware.
- The FPGA-to-ASIC gap is a well-known trap: Redwood has not been taped out, and Architect Labs' own roadmap treats the tapeout as the real test, not the FPGA demo.
What to watch next
- TSMC tapeout announcement: Architect Labs says it is working toward a TSMC tapeout; post-silicon validation results will confirm or collapse the 3.4x performance claim.
- Whether the 48-hour respec capability holds at larger model scales and more complex fabrics, the next stated milestone before physical design begins.
- Competitive response from established EDA vendors and AI chip startups, who will now face pressure to show comparable AI-driven design automation timelines.
Originally published on Present of AI, a daily source-linked AI news timeline. Read the full timeline or browse the open dataset.